An address transition detection circuit for use on an address bus having any number of addresses is disclosed in U.S. Pat. No. 5,875,152, issued on Feb. 23, 1999, and entitled “Address Transition Detection Circuit for a Semiconductor Memory Capable of Detecting Narrowly Spaced Address Changes.” This patent discloses a circuit that provides an ATD circuit which detects each address transition and provides an ATD circuit suitable for use with memories having address buses with a large number of addresses. As shown in FIG. 1, an edge detect unit 100 in the prior art comprises a minimum delay unit 106 and a comparator 108. Minimum delay unit 106 outputs the AIs (Input Address signal) in delayed form to comparator 108. Comparator 108 detects an address transition by responding to both the original AIs and the delayed AIs on its inputs. In the prior art, a minimum delay unit 106 is required for each address in a plurality of addresses. Accordingly, the circuit requires a large area on the chip for all the minimum delay units.
What is needed is an address transition detection circuit that does not use the minimum delay unit required for each address line, as in the prior art, and thereby can save a area in the layout of the integrated circuit.